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HN58V65AI Series HN58V66AI Series HN58V65A-SR Series HN58V66A-SR Series
64k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A) Wide Temperature Range version
REJ03C0153-0300Z (Previous ADE-203-759B(Z) Rev.2.0) Rev. 3.00 Feb.02.2004
Description
Renesas Technology's HN58V65A series and HN58V66A series are electrically erasable and programmable EEPROM's organized as 8192-word x 8-bit. They have realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.
Features
* Single supply: 2.7 to 5.5 V * Access time: 100 ns (max) at 2.7 V VCC < 4.5 V 70 ns (max) at 4.5 V VCC 5.5 V * Power dissipation: Active: 20 mW/MHz (typ) Standby: 110 W (max) * On-chip latches: address, data, CE, OE, WE * Automatic byte write: 10 ms (max) * Automatic page write (64 bytes): 10 ms (max) * Ready/Busy * Data polling and Toggle bit * Data protection circuit on power on/off
Rev.3.00, Feb.02.2004, page 1 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Features (cont)
* * * * * * * Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page mode) 10 years data retention Software data protection Write protection by RES pin (only the HN58V66A series) Operating temperature range: HN58V65AI/HN58V66AI Series: -40 to +85C HN58V65A-SR/HN58V66A-SR Series: -20 to +85C * There are also lead free products.
Ordering Information
Access time Type No. HN58V65API-10 HN58V66API-10 HN58V65AFPI-10 HN58V66AFPI-10 HN58V65ATI-10 HN58V66ATI-10 HN58V65AT-10SR HN58V66AT-10SR HN58V65API-10E HN58V66API-10E 2.7 V VCC < 4.5 V 4.5 V VCC 5.5 V Package 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 600 mil 28-pin plastic DIP (DP-28V) Lead free 400 mil 28-pin plastic SOP (FP-28DV) Lead free 28-pin plastic TSOP(TFP-28DBV) Lead free 28-pin plastic TSOP(TFP-28DB) 400 mil 28-pin plastic SOP (FP-28D) 600 mil 28-pin plastic DIP (DP-28)
HN58V65AFPI-10E 100 ns HN58V66AFPI-10E 100 ns HN58V65ATI-10E HN58V66ATI-10E 100 ns 100 ns
HN58V65AT-10SRE 100 ns HN58V66AT-10SRE 100 ns
Rev.3.00, Feb.02.2004, page 2 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Pin Arrangement
HN58V65API Series HN58V65AFPI Series RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) HN58V66API Series HN58V66AFPI Series RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE RES A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
HN58V65ATI Series HN58V65AT-SR Series
A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE NC A8 A9 A11 OE
(Top view)
HN58V66ATI Series HN58V66AT-SR Series
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE RES A8 A9 A11 OE
(Top view)
Rev.3.00, Feb.02.2004, page 3 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Pin Description
Pin name A0 to A12 I/O0 to I/O7 OE CE WE VCC VSS RDY/Busy RES*1 NC Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground Ready busy Reset No connection
Note: 1. This function is supported by only the HN58V66A series.
Block Diagram
Note: 1. This function is supported by only the HN58V66A series.
VCC VSS RES *1 OE CE WE RES *1 A0
to
I/O0 to I/O7 High voltage generator
RDY/Busy
I/O buffer and input latch Control logic and timing
Y decoder Address buffer and latch
Y gating
A5
A6
to
X decoder
Memory array
A12 Data latch
Rev.3.00, Feb.02.2004, page 4 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Operation Table
Operation Read Standby Write Deselect Write Inhibit Data Polling Program reset CE VIL VIH VIL VIL x x VIL x OE VIL x*
2
WE VIH x VIL VIH VIH x VIH x
RES*3 VH* x VH VH x x VH VIL
1
RDY/Busy High-Z High-Z High-Z to VOL High-Z VOL High-Z
I/O Dout High-Z Din High-Z Dout (I/O7) High-Z
VIH VIH x VIL VIL x
Notes: 1. Refer to the recommended DC operating conditions. 2. x : Don't care 3. This function supported by only the HN58V66A series.
Absolute Maximum Ratings
Parameter Power supply voltage relative to VSS Input voltage relative to VSS Operating temperature range *2 HN58V65AI/HN58V66AI Symbol VCC Vin Topr Value -0.6 to +7.0 -0.5* to +7.0*3 -40 to +85 -20 to +85 -55 to +125
1
Unit V V C C C
HN58V65A-SR/HN58V66A-SR Topr Storage temperature range Notes: 1. Vin min : -3.0 V for pulse width 50 ns. 2. Including electrical characteristics and data retention. 3. Should not exceed VCC + 1 V. Tstg
Rev.3.00, Feb.02.2004, page 5 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Recommended DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input voltage VIL VIH VH*
4
Min 2.7 0 -0.3* 2.4*
2 1
Typ -- 0 -- --
Max 5.5 0 0.6*
5 3
Unit V V V V V C C
VCC + 0.3* VCC + 1.0 +85 +85
VCC - 0.5 -- HN58V65AI/HN58V66AI HN58V65A-SR/HN58V66A-SR -40 -20 -- --
Operating temperature Topr Notes: 1. 2. 3. 4. 5.
VIL min: -1.0 V for pulse width 50 ns. VIH = 3.0 V for VCC = 3.6 to 5.5 V. VIH max: VCC + 1.0 V for pulse width 50 ns. This function is supported by only the HN58V66A series. VIL = 0.8 V for VCC = 3.6 V to 5.5 V
DC Characteristics
(Ta = -40 to +85C, VCC = 2.7 to 5.5 V: HN58V66AI/HN58V66AI, Ta = -20 to +85C, VCC = 2.7 to 5.5 V: HN58V66A-SR/HN58V66A-SR)
Parameter Input leakage current Output leakage current Standby VCC current Operating VCC current Symbol ILI ILO ICC1 ICC2 ICC3 Min Output low voltage Output high voltage Note: VOL VOH Typ 1 to 2 Max 2* 2 5 1 6 10 15 25 0.4
1
Unit A A A mA mA mA mA mA V V
Test conditions VCC = 5.5 V, Vin = 5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 5.5 V Iout = 0 mA, Duty = 100%, Cycle = 100 ns at VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 70 ns at VCC = 5.5 V IOL = 2.1 mA IOH = -400 A
VCC x 0.8
1. ILI on RES : 100 A max (only the HN58V66A series)
Rev.3.00, Feb.02.2004, page 6 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Capacitance (Ta = +25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Note: Symbol Cin*
1 1
Min
Typ
Max 6 12
Unit pF pF
Test conditions Vin = 0 V Vout = 0 V
Cout*
1. This parameter is sampled and not 100% tested.
AC Characteristics
(Ta = -40 to +85C, VCC = 2.7 to 5.5 V: HN58V65AI/HN58V66AI, Ta = -20 to +85C, VCC = 2.7 to 5.5 V: HN58V65A-SR/HN58V66A-SR) Test Conditions * Input pulse levels : * * * * 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V) 0 V to VCC (RES pin*2) Input rise and fall time : 5 ns Input timing reference levels : 0.8, 1.8 V Output load : 1TTL Gate +100 pF Output reference levels : 1.5 V, 1.5 V
Read Cycle 1 (2.7 VCC < 4.5 V)
HN58V65AI/HN58V66AI HN58V65A-SR/HN58V66A-SR -10 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float*1, 2 RES to output delay*
2 1
Symbol tACC tCE tOE tOH tDF tDFR tRR
Min 10 0 0 0 0
Max 100 100 50 40 350 450
Unit Test conditions ns ns ns ns ns ns ns CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE= VIL, WE = VIH
Rev.3.00, Feb.02.2004, page 7 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Write Cycle 1 (2.7 VCC < 4.5 V)
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time*
2, 6 2
Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES
Min*3 0 50 0 0 0 0 0 0 50 0 200 200 100 0.3 100 120 0*
5
Typ
Max 30 10*
4
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns s s
Test conditions
100 1
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A series. 3. Use this device in longer cycle than this value. 4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE. 8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics.
Rev.3.00, Feb.02.2004, page 8 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Read Cycle 2 (4.5 VCC 5.5 V)
HN58V65AI/HN58V66AI HN58V65A-SR/HN58V66A-SR -10 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float* RES to output delay*
2 1, 2 1
Symbol tACC tCE tOE tOH tDF tDFR tRR
Min 10 0 0 0 0
Max 70 70 40 30 350 450
Unit Test conditions ns ns ns ns ns ns ns CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE= VIL, WE = VIH
Rev.3.00, Feb.02.2004, page 9 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Write Cycle 2 (4.5 VCC 5.5 V)
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time*
2, 6 2
Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW tRP tRES
Min*3 0 50 0 0 0 0 0 0 50 0 100 100 50 0.2 100 120 0*
5
Typ
Max 30 10*
4
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns s s
Test conditions
100 1
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A. 3. Use this device in longer cycle than this value. 4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 6. This parameter is sampled and not 100% tested. 7. A6 through A12 are page address and these addresses are latched at the first falling edge of WE. 8. A6 through A12 are page address and these addresses are latched at the first falling edge of CE. 9. See AC read characteristics.
Rev.3.00, Feb.02.2004, page 10 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Timing Waveforms
Read Timing Waveform
Address tACC CE tCE OE tOE WE High tDF tOH
Data Out tRR
Data out valid tDFR
RES *2
Rev.3.00, Feb.02.2004, page 11 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Byte Write Timing Waveform(1) (WE Controlled)
tWC Address tCS CE tAS WE tOES OE tDS Din tDW RDY/Busy High-Z tRP tDB High-Z tDH tOEH tBL tAH tCH
tWP
tRES RES *2 VCC
Rev.3.00, Feb.02.2004, page 12 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Byte Write Timing Waveform(2) (CE Controlled)
Address tWS CE tAS WE tOES OE tDS Din tDW High-Z tRP tRES RES *2 tDB High-Z tDH tOEH tAH tCW tWH tBL tWC
RDY/Busy
VCC
Rev.3.00, Feb.02.2004, page 13 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Page Write Timing Waveform(1) (WE Controlled)
*7
Address A0 to A12 WE
tAS
tAH tWP tDL tBLC
tBL
tCS CE tOES OE
tCH
tWC
tOEH tDH
tDS
Din tDB tDW High-Z
RDY/Busy
High-Z
tRP RES *2
tRES
VCC
Rev.3.00, Feb.02.2004, page 14 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Page Write Timing Waveform(2) (CE Controlled)
*8
Address A0 to A12 CE
tAS
tAH tCW tDL tBLC
tBL
tWS WE
tWH
tWC
tOEH tOES OE tDH tDS
Din tDB tDW High-Z
RDY/Busy
High-Z
tRP RES *2
tRES
VCC
Rev.3.00, Feb.02.2004, page 15 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Data Polling Timing Waveform
Address
An
An
An
CE
WE
tOEH
tCE *9
tOES
OE tOE*9 I/O7 Din X Dout X Dout X tWC tDW
Rev.3.00, Feb.02.2004, page 16 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Toggle Bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle Bit Waveform Notes: 1. 2. 3. 4. I/O6 beginning state is "1". I/O6 ending state will vary. See AC read characteristics. Any address location can be used, but the address must be fixed.
Next mode
*4
Address tCE *3
CE
WE tOE tOEH
*1 *2 *2
*3
OE
tOES
I/O6
Din
Dout
Dout tWC
Dout
Dout tDW
Rev.3.00, Feb.02.2004, page 17 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Software Data Protection Timing Waveform(1) (in protection mode)
VCC
CE
WE tBLC Address Data 1555 AA 0AAA 55 1555 A0 Write address Write data tWC
Software Data Protection Timing Waveform(2) (in non-protection mode)
VCC
tWC
Normal active mode
CE
WE
Address Data
1555 0AAA 1555 1555 0AAA 1555 AA 55 80 AA 55 20
Rev.3.00, Feb.02.2004, page 18 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Functional Description
Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES Signal (only the HN58V66A series) When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn't provide a latch function.
VCC
Read inhibit
Read inhibit
RES
Program inhibit
Program inhibit
Rev.3.00, Feb.02.2004, page 19 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Protection To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 15 ns or less. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. Be careful not to allow noise of a width of more than 15 ns on the control pins.
WE CE VIH 0V
OE
VIH 0V
15 ns max
Rev.3.00, Feb.02.2004, page 20 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series 2. Data protection at VCC on/off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC CPU RESET * Unprogrammable
* Unprogrammable
2.1 Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE OE WE x: Don't care. VCC: Pull-up to VCC level. VSS: Pull-down to VSS level. VCC x x x VSS x x x VCC
Rev.3.00, Feb.02.2004, page 21 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series 2.2 Protection by RES (only the HN58V66A series) The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.
VCC
RES Program inhibit WE or CE Program inhibit
1 s min 100 s min
10 ms min
Rev.3.00, Feb.02.2004, page 22 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series 3. Software data protection To prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. In software data protection mode, 3 bytes of data must be input before write data as follows. And these bytes can switch the non-protection mode to the protection mode. SDP is enabled if only the 3 byte code is input.
Address Data
1555 AA 0AAA 55 1555 A0 Write address Write data } Normal data input
Software data protection mode can be canceled by inputting the following 6 bytes. After that, this device turns to the non-protection mode and can write data normally. But when the data is input in the canceling cycle, the data cannot be written.
Address 1555 0AAA 1555 1555 0AAA 1555 Data AA 55 80 AA 55 20
The software data protection is not enabled at the shipment. Note: There are some differences between Renesas Technology's and other company's for enable/disable sequence of software data protection. If there are any questions, please contact with Renesas Technology's sales offices.
Rev.3.00, Feb.02.2004, page 23 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Package Dimensions
HN58V65API Series HN58V66API Series (DP-28, DP-28V)
Unit: mm
15
28
35.6 36.5 Max
1
1.2
1.9 Max
14
13.4 14.6 Max
0.51 Min
2.54 Min 5.70 Max
15.24
0.25 - 0.05 0 - 15
+ 0.11
2.54 0.25
0.48 0.10
Package Code JEDEC JEITA Mass (reference value)
DP-28, DP-28V -- Conforms 4.6 g
Rev.3.00, Feb.02.2004, page 24 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Package Dimensions (cont)
HN58V65AFPI Series HN58V66AFPI Series (FP-28D, FP-28DV)
Unit: mm
18.3 18.8 Max 28 15
8.4
1.12 Max
*0.17 0.05 0.15 0.04
1
14
2.50 Max
11.8 0.3 1.7 0 - 8
1.27 0.15
*0.40 0.08 0.38 0.06
0.20 0.10
1.0 0.2
0.20 M
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass (reference value)
FP-28D, FP-28DV Conforms -- 0.7 g
Rev.3.00, Feb.02.2004, page 25 of 26
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Package Dimensions (cont)
HN58V65ATI Series HN58V66ATI Series HN58V65AT-SR Series HN58V66AT-SR Series (TFP-28DB, TFP-28DBV)
Unit: mm
8.00 8.20 Max 28 15
1
14 0.55
*0.22 0.08 0.10 M 0.20 0.06 0.45 Max
11.80
13.40 0.30 0 - 5
0.80
*0.17 0.05 0.15 0.04
1.20 Max
0.10
0.13 -0.08
+0.07
0.50 0.10
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass (reference value)
TFP-28DB, TFP-28DBV -- -- 0.23 g
Rev.3.00, Feb.02.2004, page 26 of 26
Revision History HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series Data Sheet
Rev. Date Contents of Modification Page 0.0 1.0 Mar. 12, 1997 Aug. 29, 1997 7 11 19 2.0 3.00 Oct. 31, 1997 Feb. 02, 2004 6 2 Description Initial issue Addition of HN58V65A-SR/HN58V66A-SR AC Characteristics Input pulse level: 0.4 V to VCC to 0 V to VCC Timing Waveform Read Timing Waveform: Correct error Functional Description Data Protection 3.: Addition of description DC Characteristics ICC3 (max): 6/10/12/25 mA to 6/10/15/25 mA
Ordering Information Addition of HN58V65API-10E, HN58V66API-10E, HN58V65AFPI-10E, HN58V66AFPI-10E, HN58V65ATI-10E, HN58V66ATI-10E, HN58V65AT-10SRE, HN58V66AT-10SRE 24-26 Package Dimensions DP-28 to DP-28, DP-28V FP-28D to FP-28D, FP-28DV TFP-28DB to TFP-28DB, TFP-28DBV
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001
http://www.renesas.com
(c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
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